1. Field of the Invention
The present invention relates to an arrangement for translating logical (or virtual) page addresses into corresponding real ones in data processing systems using virtual memory techniques.
2. Description of the Prior Art
A so-called supercomputer has found extensive uses in high speed mathematical or scientific tasks such as in weather forecast simulation, image data processing for natural resources, etc. It is known in the art that such a very powerful mainframe adopts high-level operations that work on vectors (viz., linear arrays of numbers) utilizing a virtual memory technique. The virtual memory is a large imaginary main memory made available by loading smaller pages from a backing store into a main memory as they are required.
The mechanism used to define the relationship between the logical (or virtual) address space that the program thinks it is controlling, and the actual main memory locations being utilized, is called an "address translation".
In order to accelerate the page address translation, it is a common practice to prepare one or more address translation buffers into which a page address translation table(s) has previously been transferred from a main memory.
One known approach to performing high-speed page address translation, is to translate all the logical page addresses at a time by preparing a plurality of address translation buffers, the number of which is equal to the entire number of logical pages. Although this method is able to attain the address translation at a high speed and hence a high throughput, it has encountered the problem in that a bulky hardware arrangement is undesirably required.
Another known approach is to prepare a plurality of address translation buffers and then implement address translation of a plurality of consecutive logical pages at a time according to a heading number of the consecutive logical pages to be translated and a direction (increasing or decreasing direction) of the consecutive page numbers. This prior art has been disclosed in Japanese patent application publication No. 63-62012 issued for public inspection on Dec. 1, 1988. This prior art features an effective address translation without an undesirable increase in hardware, but has encountered the problem in that it is unable to implement address translation of a plurality of logical pages at any given time if a program requires random logical pages in the case of indirect addressing.